? semiconductor components industries, llc, 2002 july, 2002 rev. 0 1 publication order number: and8089/d and8089/d determining the free-running frequency for qr systems christophe basso on semiconductor 14, rue paul mespl bp1112 31035 toulouse cedex 1 france 33 (0)5 34 61 11 54 email: christophe.basso@onsemi.com introduction a quasisquare wave switchmode power supply offers many advantages such as a soft emi signature and a constant efficiency over a broad output load range. however, by nature, a quasiresonant (qr) supply exhibits a highly variable switching frequency which depends on the input / output operating conditions. this short application note details how to evaluate the switching frequency at a given operating point and thus gives the designer the necessary insight to dimension his system. a flyback working in qr mode a flyback working in qr mode is nothing else than a standard pwmdriven flyback circuit to which a resonating tank has been added. figure 1 shows the basic configuration of a converter that could be controlled through a dedicated circuit like on semiconductor ncp1205 or NCP1207. on this circuit, the resonating tank is made of l p c p , the primary inductance and the resonating capacitor. when the switch closes, the current buildsup in the primary inductance and the drain voltage is close to zero. at the switch opening, the leakage inductance together with c p dictate the rising slope of the drain voltage. when the leakage inductance is reset, the drain reaches a plateau made of v in plus the reflected output voltage vr. finally, when the core is fully reset, a damped oscillation takes place on the drain and successive avalleyso (minimal) appear. if the reflected voltage is selected to be strong enough compared to v in (ideal is when vr = v in ), then the mosfet can be restarted with a null drainsource voltage, minimizing all associated capacitive losses: this is called zerovoltage switching (zvs) operation. the ademago winding offers an image of the core's flux and helps to detect the reset event (when iprimary = 0). unfortunately, zvs can only be obtained if sufficient voltage is reflected on the drain. figure 2 portrays a typical signal where the reflected voltage vr, is too low compared to v in . when operating on universal mains up to 275 vac, tradeoffs have to be made to ensure zvs operation at high line but also to limit the mosfet bvdss to a reasonable value (a cost sensitive parameter ). an 800 v device, for instance, can be a good choice to allow qr operation over a large portion of the universal mains, for instance on a single output power supply. 1 2 l p c p leakage valleys v in vr demag lleak cp 1:n qr controller + + v in v out figure 1. a qr flyback converter figure 2. a typical drainsource signal of a qr converter application note http://onsemi.com
and8089/d http://onsemi.com 2 a succession of events to calculate the operating frequency of a qr converter, one needs to account for all the parasitic elements involved in the structure. for example, the leakage inductance plays a significant role in slowing down the drainsource signal. neglecting it leads to a large error, especially if the resonating capacitor has been increased to reduce the dvds/dt and avoid a clamping network. to fully understand the time sequences, figure 3 shows a qr converter truly operating in zvs. are present on this picture the drainsource signal vds(t), the internal primary inductance current iprimary(t) and the driver waveshape to detail exactly when the mosfet is reactivated. to the light of this picture, it can be noticed that the primary current iprimary(t) and vds(t) being in quadrature, switching the mosfet when vds(t) equals zero also engenders zero current switching (zcs)! however, care must be taken to introduce the proper delay when core reset is detected. if this delay is too long or too short, then zvs/zcs can no longer be maintained and losses increase vds = 200 v / div = 200 ma / div x = 3.67 s / div 0 vds core is reset! figure 3. a converter truly working in zvs with a smooth vds transition i p lleak c p v in n (v out v f ) t on tl t off t w i p let's review, one by one, the events shown on figure 3: t on : the switch closes, forcing a voltage (v in ) across the primary inductance l p . the current increases with a slope of: (eq. 1) v in l p when i p is reached, the controller dictates the opening of the switch. therefore, t on is equal to: t on i p l p v in (eq. 2) with: l p the primary inductance, v in the input voltage, i p the peak current. tleak: at the switch opening, the voltage cannot instantaneously increase and the perfidious leakage inductance delays the transfer of the primary current to the secondary. vds rises with a slope imposed by the peak current present at the switch opening: vds(t) slope is: (eq. 3) i p c p if we neglect all other capacitance at the drain node. the peak voltage is given by the characteristic impedance of the resonating tank made by lleak and c p : (eq. 4) vds max i p lleak c p v in n (v out v f ) the secondary diode starts to conduct at the time vds(t) reaches n x (v out + v f ). therefore, combining eq. 3 and eq. 4, we obtain the arisingo time: (eq. 5) tl [i p lleak c p v in n (v out v f )] c p i p with: vout the output voltage, vf the diode's forward drop, n the n p /ns turn ratio, lleak the leakage inductance, c p the resonating capacitor.
and8089/d http://onsemi.com 3 t off : t off represents the time needed to bring the peak current back to zero through the reflected voltage applied over l p . therefore, t off can easily be derived: (eq. 6) t off i p l p n (v out v f) with: v out the output voltage, v f the diode's forward drop, n the n p /ns turn ratio tw: without entering into complex calculations, one can see that the valley occurs at half the natural ringing period imposed by l p and c p . tw is thus defined by: (eq. 7) tw l p c p however, when complete calculations are undertaken, it shows that this result is only valid for lightly damped resonating tanks, which is often the case. we now have everything needed to compute the switching frequency by summing up all these events and reversing the result: (eq. 8) fsw 1 i p l p v in [i p lleak c p v in n (v out v f )] c p i p i p l p n (v out v f ) l p c p the unknown equation remains the peak current i p . to obtain it, we need to start from the classical flyback power transfer formula: (eq. 9) p out n 1 2 l p i p 2 fsw rearranging it gives: (eq. 10) i p 2 p out l p fsw now, let's plug equation 10 into equation 8 to obtain a third order equation of i p : (eq. 11) i p 2 2 p out l p [ l p v in i p l p n (v out v f ) i p l p c p (i p lleak c p v in n (v 0 v f )) c p i p ] this third order equation can be examined with a mathematical solver to obtain a rather complicated formula: (eq. 12) i p 1 6 36 i1 io 2 108 i2 io 8 io 3 12 3 io 2 ( 4 i1 3 io i1 2 io 2 18 i1 io i2 27 i2 2 4 12 io 2 ) 12 i1 io 4 io 2 [36 i1 io 2 108 i2 io 8 io 3 12 3 io 2 ( 4 i1 3 io i1 2 io 2 18 i1 io i2 27 i2 2 4 i2 io 2 ] 1 3 1 io 3 with : a c p l p b lleak l p i1 a (1 b) v in vr v in vr i2 a 2 (v in vr) i o 2 p out (v in vr) v in vr once i p is known, the switching frequency can be computed via equation 8.
and8089/d http://onsemi.com 4 to ease the designer work, we have entered this formula into an excel spreadsheet available to download from on semiconductor web site (www.onsemi.com), ncp1205 or NCP1207 related sections. by entering the power supply parameters, you can quickly view the evolution of the switching frequency with the selected primary inductance l p , the input voltage or select the inductance that brings the desired switching frequency in worse case conditions, e.g. highest output power and lowest input line. below are some typical curves given by the spreadsheet for a 30 w smps featuring the following component values: l p = 1.4 mh lleak = 15 h v out = 16.8 v p out = 30 w n p : ns = 16.6 c p = 1.5 nf 0.200 0.300 0.400 0.500 0.600 0.700 0.800 0.900 1.000 1.100 120 170 220 270 320 370 input voltage (v) primary peak current (a) 0.000 0.050 0.100 0.150 0.200 0.250 0.300 0.350 0.400 0.450 0.500 primary rms current (a) figure 4. peak current vs. input voltage primary current evolution with the input voltage 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 5.0e04 1.0e03 1.5e03 2.0e03 2.5e03 3.0e03 primary inductance switching frequency (khz) 0.410 0.420 0.425 0.430 0.435 0.440 0.445 primary rms current (a) figure 5. freerunning frequency vs. l p . (this graph lets you select the inductance value that will bring the desired frequency at low line) 0.415 i ppeck i prms i prms f switching
and8089/d http://onsemi.com 5 to check our calculations, the above 30 w prototype has been built using the ncp1205, a new qr controller featuring a soft frequency foldback with a voltage controller oscillator. it is very important to ensure true valley switching, e.g. starting right in the middle of the wave, or the above equations are no longer valid. the below graph compares the frequency variation with the input voltage measured on the board or calculated: figure 6. switching frequency vs. v in @ p out = 30 w 30 40 50 60 70 80 90 120 170 220 270 320 input line (dc) switching frequency (khz) calculated measured as one can see, both graphs are in good agreement and the highline error is better than 10%, confirming the validity of our assumptions. the complete description of the board is the object of a dedicated application note, also available from the on semiconductor web site, ncp1205 and NCP1207 related sections. acknowledgements the author wishes to thank his colleagues fran?ois lhermite and jo?l turchi for fruitful discussions related to quasiresonant converters.
and8089/d http://onsemi.com 6 notes
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